Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
98 lines
2.5 KiB
C
98 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ASM_UACCESS_H
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#define __ASM_ASM_UACCESS_H
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#include <asm/alternative-macros.h>
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#include <asm/asm-extable.h>
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#include <asm/assembler.h>
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#include <asm/kernel-pgtable.h>
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#include <asm/mmu.h>
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#include <asm/sysreg.h>
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/*
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* User access enabling/disabling macros.
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*/
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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.macro __uaccess_ttbr0_disable, tmp1
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mrs \tmp1, ttbr1_el1 // swapper_pg_dir
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bic \tmp1, \tmp1, #TTBR_ASID_MASK
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sub \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET // reserved_pg_dir
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msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
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add \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET
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msr ttbr1_el1, \tmp1 // set reserved ASID
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isb
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.endm
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.macro __uaccess_ttbr0_enable, tmp1, tmp2
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get_current_task \tmp1
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ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1
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mrs \tmp2, ttbr1_el1
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extr \tmp2, \tmp2, \tmp1, #48
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ror \tmp2, \tmp2, #16
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msr ttbr1_el1, \tmp2 // set the active ASID
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msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1
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isb
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.endm
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.macro uaccess_ttbr0_disable, tmp1, tmp2
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alternative_if_not ARM64_HAS_PAN
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save_and_disable_irq \tmp2 // avoid preemption
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__uaccess_ttbr0_disable \tmp1
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restore_irq \tmp2
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alternative_else_nop_endif
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.endm
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.macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
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alternative_if_not ARM64_HAS_PAN
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save_and_disable_irq \tmp3 // avoid preemption
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__uaccess_ttbr0_enable \tmp1, \tmp2
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restore_irq \tmp3
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alternative_else_nop_endif
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.endm
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#else
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.macro uaccess_ttbr0_disable, tmp1, tmp2
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.endm
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.macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
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.endm
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#endif
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#define USER(l, x...) \
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9999: x; \
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_asm_extable_uaccess 9999b, l
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#define USER_CPY(l, uaccess_is_write, x...) \
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9999: x; \
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_asm_extable_uaccess_cpy 9999b, l, uaccess_is_write
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/*
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* Generate the assembly for LDTR/STTR with exception table entries.
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* This is complicated as there is no post-increment or pair versions of the
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* unprivileged instructions, and USER() only works for single instructions.
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*/
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.macro user_ldp l, reg1, reg2, addr, post_inc
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8888: ldtr \reg1, [\addr];
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8889: ldtr \reg2, [\addr, #8];
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add \addr, \addr, \post_inc;
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_asm_extable_uaccess 8888b, \l;
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_asm_extable_uaccess 8889b, \l;
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.endm
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.macro user_stp l, reg1, reg2, addr, post_inc
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8888: sttr \reg1, [\addr];
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8889: sttr \reg2, [\addr, #8];
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add \addr, \addr, \post_inc;
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_asm_extable_uaccess 8888b,\l;
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_asm_extable_uaccess 8889b,\l;
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.endm
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.macro user_ldst l, inst, reg, addr, post_inc
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8888: \inst \reg, [\addr];
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add \addr, \addr, \post_inc;
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_asm_extable_uaccess 8888b, \l;
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.endm
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#endif
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