Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/***************************************************************************
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* Header for plx9050 pci chip
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* copyright : (C) 2002 by Frank Mori Hess
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***************************************************************************/
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#ifndef _PLX9050_GPIB_H
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#define _PLX9050_GPIB_H
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// plx pci chip registers and bits
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enum {
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PLX9050_INTCSR_REG = 0x4c,
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PLX9050_CNTRL_REG = 0x50
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};
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enum plx9050_intcsr_bits {
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PLX9050_LINTR1_EN_BIT = 0x1,
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PLX9050_LINTR1_POLARITY_BIT = 0x2,
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PLX9050_LINTR1_STATUS_BIT = 0x4,
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PLX9050_LINTR2_EN_BIT = 0x8,
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PLX9050_LINTR2_POLARITY_BIT = 0x10,
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PLX9050_LINTR2_STATUS_BIT = 0x20,
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PLX9050_PCI_INTR_EN_BIT = 0x40,
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PLX9050_SOFT_INTR_BIT = 0x80,
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PLX9050_LINTR1_SELECT_ENABLE_BIT = 0x100, // 9052 extension
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PLX9050_LINTR2_SELECT_ENABLE_BIT = 0x200, // 9052 extension
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PLX9050_LINTR1_EDGE_CLEAR_BIT = 0x400, // 9052 extension
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PLX9050_LINTR2_EDGE_CLEAR_BIT = 0x800, // 9052 extension
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};
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enum plx9050_cntrl_bits {
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PLX9050_WAITO_NOT_USER0_SELECT_BIT = 0x1,
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PLX9050_USER0_OUTPUT_BIT = 0x2,
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PLX9050_USER0_DATA_BIT = 0x4,
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PLX9050_LLOCK_NOT_USER1_SELECT_BIT = 0x8,
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PLX9050_USER1_OUTPUT_BIT = 0x10,
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PLX9050_USER1_DATA_BIT = 0x20,
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PLX9050_CS2_NOT_USER2_SELECT_BIT = 0x40,
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PLX9050_USER2_OUTPUT_BIT = 0x80,
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PLX9050_USER2_DATA_BIT = 0x100,
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PLX9050_CS3_NOT_USER3_SELECT_BIT = 0x200,
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PLX9050_USER3_OUTPUT_BIT = 0x400,
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PLX9050_USER3_DATA_BIT = 0x800,
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PLX9050_PCIBAR_ENABLE_MASK = 0x3000,
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PLX9050_PCIBAR_MEMORY_AND_IO_ENABLE_BITS = 0x0,
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PLX9050_PCIBAR_MEMORY_NO_IO_ENABLE_BITS = 0x1000,
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PLX9050_PCIBAR_IO_NO_MEMORY_ENABLE_BITS = 0x2000,
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PLX9050_PCIBAR_MEMORY_AND_IO_TOO_ENABLE_BITS = 0x3000,
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PLX9050_PCI_READ_MODE_BIT = 0x4000,
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PLX9050_PCI_READ_WITH_WRITE_FLUSH_MODE_BIT = 0x8000,
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PLX9050_PCI_READ_NO_FLUSH_MODE_BIT = 0x10000,
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PLX9050_PCI_READ_NO_WRITE_MODE_BIT = 0x20000,
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PLX9050_PCI_WRITE_MODE_BIT = 0x40000,
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PLX9050_PCI_RETRY_DELAY_MASK = 0x780000,
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PLX9050_DIRECT_SLAVE_LOCK_ENABLE_BIT = 0x800000,
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PLX9050_EEPROM_CLOCK_BIT = 0x1000000,
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PLX9050_EEPROM_CHIP_SELECT_BIT = 0x2000000,
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PLX9050_WRITE_TO_EEPROM_BIT = 0x4000000,
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PLX9050_READ_EEPROM_DATA_BIT = 0x8000000,
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PLX9050_EEPROM_VALID_BIT = 0x10000000,
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PLX9050_RELOAD_CONFIG_REGISTERS_BIT = 0x20000000,
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PLX9050_PCI_SOFTWARE_RESET_BIT = 0x40000000,
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PLX9050_MASK_REVISION_BIT = 0x80000000
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};
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static inline unsigned int PLX9050_PCI_RETRY_DELAY_BITS(unsigned int clocks)
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{
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return ((clocks / 8) << 19) & PLX9050_PCI_RETRY_DELAY_MASK;
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}
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#endif // _PLX9050_GPIB_H
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