Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/*
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* Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer
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* driver.
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*
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* Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
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* --------------------------------------------------------------------------
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* $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $
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* --------------------------------------------------------------------------
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#ifndef CVISIONPPC_H
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#define CVISIONPPC_H
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#ifndef PM2FB_H
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#include "pm2fb.h"
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#endif
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struct cvppc_par {
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unsigned char* pci_config;
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unsigned char* pci_bridge;
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u32 user_flags;
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};
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#define CSPPC_PCI_BRIDGE 0xfffe0000
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#define CSPPC_BRIDGE_ENDIAN 0x0000
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#define CSPPC_BRIDGE_INT 0x0010
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#define CVPPC_PCI_CONFIG 0xfffc0000
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#define CVPPC_ROM_ADDRESS 0xe2000001
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#define CVPPC_REGS_REGION 0xef000000
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#define CVPPC_FB_APERTURE_ONE 0xe0000000
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#define CVPPC_FB_APERTURE_TWO 0xe1000000
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#define CVPPC_FB_SIZE 0x00800000
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#define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
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#define CVPPC_MEM_CONFIG_NEW 0xed41c532 /* FIXME USA?? */
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#define CVPPC_MEMCLOCK 83000 /* in KHz */
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/* CVPPC_BRIDGE_ENDIAN */
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#define CSPPCF_BRIDGE_BIG_ENDIAN 0x02
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/* CVPPC_BRIDGE_INT */
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#define CSPPCF_BRIDGE_ACTIVE_INT2 0x01
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#endif /* CVISIONPPC_H */
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/*****************************************************************************
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* That's all folks!
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*****************************************************************************/
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